1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods that involve multi-polygon constraint decomposition when using double patterning techniques to manufacture integrated circuit products.
2. Description of the Related Art
Integrated circuit products, or ICs, are generally created by patterning several layers of material so as to define the various devices and components, e.g., transistors, resistors, capacitors, etc., that are used to make the product. Generally, the process starts with the design of the integrated circuit using electronic design automation (EDA) tools that allow a designer to interactively position and connect various components of the overall circuit. This design, in turn, is generated into a circuit layout by the electronic design automation tool. The circuit layout, also known simply as a layout, contains the physical locations and dimensions of the circuit's components, interconnections and various layers of the product. The components, interconnections and various layers of the circuit form the features of the integrated circuit. As noted above, the integrated circuit design is eventually fabricated by transferring the circuit layout to a semiconductor substrate in a series of layers that collectively will form the features that constitute the devices that make up the components of the integrated circuit. However, before the layout can be fabricated, a validation process of the circuit layout must take place to insure that it can actually be fabricated using existing tools and techniques.
Design Rule Checking (DRC) is the area of electronic design automation (EDA) that determines whether the physical layout of a particular chip layout satisfies a series of recommended parameters called design rules. Design rule checking is a major step during physical verification of the chip design. At a very high level, design rules are a series of parameters provided by a semiconductor manufacturer that establish certain spacing relationships between adjacent structures so that the circuit layout can actually be manufactured using existing tools and techniques. The design rules enable the chip designer to verify the manufacturability of a product layout and the mask sets (reticles) used in manufacturing the integrated circuit product. Advanced processes and products may involve the use of more restrictive design rules in an effort to improve product yield.
Design rules may be specific to a particular semiconductor manufacturing process and/or product. In general, a design rule set specifies certain geometric and connectivity restrictions between the features of the layout, e.g., gate structures, metal lines, etc., to ensure sufficient margins to account for variability in semiconductor manufacturing processes and to ensure that the circuits work as intended. Typically, there are several basic types of design rules that semiconductor manufacturers employ, e.g., width rules, spacing rules and pitch rules. A width rule specifies the smallest allowable width of any shape in the design, i.e., the width of a metal line or a gate electrode structure. A spacing rule specifies the minimum distance between two adjacent features, like the spacing between two adjacent metal lines. Spacing rules can vary depending upon the nature of the relationship between the two adjacent features, e.g., corner-to-corner spacing, tip-to-side spacing, side-to-side spacing, tip-to-tip spacing, etc. The magnitude of the space allowed by these various spacing rules will likely not be the same in all situations, e.g., the allowable tip-to-tip spacing may be different from the allowable side-to-side spacing. Additionally, the magnitude of the allowed spacing will likely be tighter (smaller) for more advanced products and processes as compared to older product generations. These single layer rules will exist for each layer of a semiconductor product, with the lowest levels typically having the tightest or most restrictive design rules and the highest metal layers on the product typically having larger, less restrictive design rules.
Typically, the design validation process is handled by a verification tool, which processes a circuit layout and verifies that the layout adheres to a set of specified design rules. One such verification tool is sometimes referred to as a design rule checker. Often times the design rule checker is implemented as a stand-alone software program, such as Cadence Assura® DRC, or as a part of an electronic design automation tool, such as Cadence Virtuoso® The design rule checker examines a layout for violations of a set of specified design rules. The layout is usually received by the design rule checker in the form of a file that digitally represents the layout of the circuit. Current formats for layout files include, but are not limited to, GDS II and OASIS. When a design rule checker observes a circuit feature within the layout that violates a particular design rule, the violation is flagged by the design rule checker. Examples of how this flagged violation can be brought to the designer's attention include, but are not limited to, marking the violation directly in a resulting output layout file or graphically bringing attention to the violation within the electronic design automation tool.
As it relates to actually manufacturing a product, photolithography is one of the basic processes used in manufacturing integrated circuit products. At a very high level, photolithography involves: (1) forming a layer of light or radiation-sensitive material, such as a photoresist material, above a layer of material or a substrate; (2) selectively exposing the radiation-sensitive material to a light generated by a light source (such as a DUV or EUV source) to transfer a pattern defined by a mask or reticle (interchangeable terms as used herein) to the radiation-sensitive material; and (3) developing the exposed layer of radiation-sensitive material to define a patterned mask layer. Various process operations, such as etching or ion implantation processes, may then be performed on the underlying layer of material or substrate through the patterned mask layer.
Of course, the ultimate goal in integrated circuit fabrication is to faithfully reproduce the final circuit layout (design) on the integrated circuit product. Historically, the pitches between features in integrated circuit products were large enough such that a desired pattern could be formed using a single patterned photoresist masking layer. However, in recent years, device dimensions and pitches have been reduced in size to the point where existing photolithography tools, e.g., 193 nm wavelength photolithography tools, cannot form a single patterned photoresist mask layer that includes all of the features of the overall target pattern. Accordingly, device designers have resorted to techniques that involve performing multiple exposures to define a single target pattern in a layer of material. One such technique is generally referred to as double patterning or double patterning technology (DPT). In general, double patterning is an exposure method that involves splitting (i.e., dividing or separating) a dense overall target circuit pattern into two separate, less-dense patterns. The simplified, less-dense patterns are then printed separately utilizing two separate photoresist masks (where one of the photoresist masks is utilized to image one of the less-dense patterns, and the other photoresist mask is utilized to image the other less-dense pattern). This technique effectively enables the printing of even smaller features than would otherwise be possible using a single photoresist mask using existing photolithography tools. There are several double patterning techniques employed by semiconductor manufacturers, all of which are well known to those skilled in the art, e.g., Litho-Litho-Etch, Litho-Etch-Litho-Etch, etc.
To use double patterning techniques, an overall target pattern must be what is referred to as double-patterning-compliant. In general, this means that an overall target pattern is capable of being decomposed into two separate patterns that each may be printed in a single layer of photoresist using existing photolithography tools. Layout designers sometimes refer to such patterns with reference to “colors.” In general, the original circuit layout may be considered to be “colorless.” During the decomposition process, a first mask will be represented in the EDA tool using a first color and the second mask will be represented in the EDA tool using a second, different color. To the extent a layout is non-double-patterning-complaint, it is sometimes stated to present a “coloring conflict” between the two masks. An overall target pattern may have many regions or areas that cannot be printed because the features in those regions are spaced too closely to one another for existing photolithography tools to be able to print such closely spaced features as individual features.
If a layout cannot be separated or “decomposed” or “colored” into two separate masks, the problem can be addressed by changing the original circuit layout. The circuit layout is usually changed manually by a designer reviewing the output from design rule checking software. However, changing a circuit layout is a time-consuming and expensive process. Additionally, a change to one portion of a circuit layout often may have the undesirable effect of changing other portions or regions of the circuit layout. A designer must evaluate many alternate fixes before determining the best solution.
While existing EDA tools and techniques are used to resolve conflicts based upon many design rules, as noted above, existing EDA tools and techniques do not resolve so-called multi-polygon constraint rules. Many of the design rules mentioned above confirm the acceptability of a circuit layout for manufacturing based upon an analysis of spacing requirement between one polygon, e.g., a metal line, and one or more adjacent polygons that are to be formed on the same mask layer. However, the manufacture of semiconductor devices is very complex and there may be situations where the manufacturability of a particular circuit layout may be adversely impacted by the proximity of a collection of polygons that are arranged in a particular pattern on a single mask layer.
For example, FIG. 1A is a simplistic depiction of one of the two colored masks that results from performing a decomposition process on an initial circuit layout (not shown). As depicted, one of the masks 10 includes a pattern of three illustrative polygons, PG1-PG3, that are in the form of vertically oriented, rectangular-shaped features, e.g., features that correspond to gate electrodes, metal lines, etc. Device manufacturers have learned that, when trying to form a pattern of three adjacent polygons (arranged side-by-side) in a single masking layer, there must be a minimum spacing 12 (a multi-polygon constraint rule, e.g., a minimum dimension (nm)) between the sides of the three adjacent polygons so that the device can be manufactured. The magnitude of the multi-polygon constraint rule will vary depending upon a variety of factors, e.g., the device under construction, the sophistication of the process tools and manufacturer, etc. Moreover, the magnitude of the multi-polygon constraint rule may be different (typically larger) depending upon the proximity of other adjacent polygons to the three polygons depicted in FIG. 1A. For example, if a horizontally-oriented line (not shown) was also positioned on the mask 10 above the three depicted polygons PG1-PG3, the magnitude of the multi-polygon constraint rule would be larger than the multi-polygon constraint rule for the case where only the three polygons are present.
FIG. 1B depicts a situation in which another decomposed mask 14 includes a four-polygon pattern, PG1-PG4. The “X” in FIG. 1B indicates a situation where the spacing between the adjacent polygons is less than the value of the multi-polygon constraint rule. Accordingly, the mask 14 cannot be manufactured. Thus, although existing EDA tools might indicate that the mask 14 shown in FIG. 1B with the four-polygon pattern PG1-PG4 can be manufactured using double patterning techniques, device manufacturers have learned that, due to the presence of the four-polygon pattern (PG1-PG4) shown in FIG. 1B (in a single mask that violates the multi-polygon constraint rule), the four-polygon pattern reflected in the mask 14 cannot be readily manufactured.
The present disclosure is directed to various methods that involve multi-polygon constraint decomposition when using double patterning techniques to manufacture integrated circuit products which may solve or at least reduce one or more of the problems identified above.